HD74LV166A Datasheet, PDF (7/10 Pages) Hitachi Semiconductor – Parallel-Load 8-bit Shift Register

HD74LV166A
Switching Characteristics (cont)
Item
Maximum clock
frequency
Propagation
delay time
Symbol
fmax
t_PLH/t_PHL
t_PHL
Setup time
t_su
Hold time
t_h
Pulse width
t_w
Ta = 25°C
Min Typ
110 165
95 125
— 6.0
— 7.7
— 5.4
— 6.9
3.5 —
3.5 —
4.5 —
4.0 —
4.0 —
1.0 —
1.0 —
1.0 —
5.0 —
4.0 —
Max
—
—
9.9
11.9
8.6
10.6
—
—
—
—
—
—
—
—
—
—
Ta = –40 to 85°C
Min
Max
Unit
90
—
MHz
85
—
1.0
11.5 ns
1.0
13.5
1.0
10.0
1.0
12.0
3.5
—
ns
3.5
—
4.5
—
4.0
—
4.0
—
1.0
—
ns
1.0
—
1.0
—
5.0
—
ns
4.0
—
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
FROM
(Input)
V_CC = 5.0 ± 0.5 V
TO
(Output)
CLK
Q_H
CLR
CLR inactive before
CLK ↑
CLK INH before CLK ↑
Data before CLK ↑
SH/LD high before CLK
↑
SER before CLK ↑
PAR data after SH/LD ↑
SER data after CLK ↑
SH/LD high after CLK ↑
CLR low
CLK H or L
Operating Characteristics
C_L = 50 pF
Ta = 25°C
Item
Symbol V_CC (V) _Min
Typ
Max
Unit Test Conditions
Power dissipation capacitance C_PD
3.3
—
36.1
—
pF
f = 10 MHz
5.0
—
37.5
—
Test Circuit
Measurement point
C_L^*
Note: C_L includes the probe and jig capacitance.
Rev.3.00 Jun. 04, 2004 page 7 of 9