HD74LV166A Datasheet, PDF (1/10 Pages) Hitachi Semiconductor – Parallel-Load 8-bit Shift Register

HD74LV166A
Parallel-Load 8-bit Shift Register
REJ03D0321–0300Z
(Previous ADE-205-268A (Z))
Rev.3.00
Jun. 04, 2004
Description
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either
in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the
Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is
asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the
clock inputs to act as a clock inhibit.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
• V_CC = 2.0 V to 5.5 V operation
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
HD74LV166AFPEL
SOP–16 pin(JEITA) FP–16DAV
FP
HD74LV166ARPEL
SOP–16 pin(JEDEC) FP–16DNV
RP
HD74LV166ATELL
TSSOP–16 pin
TTP–16DAV
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Rev.3.00 Jun. 04, 2004 page 1 of 9