3826A Datasheet, PDF (69/93 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3826 Group (A version)
Table 24 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
twH(SCLK1) Serial I/O1 clock output “H” pulse width
tC (SCLK1)/2–30
twL(SCLK1) Serial I/O1 clock output “L” pulse width
tC (SCLK1)/2–30
td(SCLK1–TXD) Serial I/O1 output delay time (Note)
tv(SCLK1–TXD) Serial I/O1 output valid time (Note)
–30
tr(SCLK1)
Serial I/O1 clock output rising time
tf(SCLK1)
Serial I/O1 clock output falling time
twH(SCLK2) Serial I/O2 clock output “H” pulse width
tC (SCLK2)/2–160
twL(SCLK2) Serial I/O2 clock output “L” pulse width
tC (SCLK2)/2–160
td(SCLK2–SOUT2) Serial I/O2 output delay time
tv(SCLK2–SOUT2) Serial I/O2 output valid time
0
tf(SCLK2)
Serial I/O2 clock output falling time
Note: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Unit
Max.
ns
ns
140
ns
ns
30
ns
30
ns
ns
ns
0.2 ✕ tC (SCLK2) ns
ns
40
ns
Table 25 Switching characteristics (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
twH(SCLK1) Serial I/O1 clock output “H” pulse width
twL(SCLK1) Serial I/O1 clock output “L” pulse width
td(SCLK1–TXD) Serial I/O1 output delay time (Note)
tv(SCLK1–TXD) Serial I/O1 output valid time (Note)
tr(SCLK1)
Serial I/O1 clock output rising time
tf(SCLK1)
Serial I/O1 clock output falling time
twH(SCLK2) Serial I/O2 clock output “H” pulse width
twL(SCLK2) Serial I/O2 clock output “L” pulse width
td(SCLK2–SOUT2) Serial I/O2 output delay time
tv(SCLK2–SOUT2) Serial I/O2 output valid time
tf(SCLK2)
Serial I/O2 clock output falling time
Limits
Min.
Typ.
tC (SCLK1)/2–100
tC (SCLK1)/2–100
–30
tC (SCLK2)/2–240
tC (SCLK2)/2–240
0
Unit
Max.
ns
ns
350
ns
ns
100
ns
100
ns
ns
ns
0.2 ✕ tC (SCLK2) ns
ns
100
ns
Note: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Measurement output pin
100 pF
CMOS output
Fig. 65 Circuit for measuring output switching characteristics
Measurement output pin
1 kΩ
100 pF
N-channel open-drain output (Note)
Note: When P71–P77, P40 and bit 4 of the UART control
register (address 001B16) is “1” (N-channel open-
drain output mode).
Rev.2.00 May. 24, 2006 page 69 of 90
REJ03B0028-0200