3826A Datasheet, PDF (31/93 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3826 Group (A version)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) is selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address (001816) in
memory. Since the shift register cannot be written to or read from
directly, transmit data is written to the transmit buffer, and receive
data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted
during transmitting, and the receive buffer register can hold re-
ceived one-byte data while the next one-byte data is being re-
ceived.
P44/RXD
P46/SCLK1
Data bus
Address 001816
Serial I/O1 control register Address 001A16
OE
Receive buffer register
Character length selection bit
STdetector 7 bits
Receive shift register
8 bits
Receive buffer full flag (RBF)
Receive interrupt request
1/16
PE FE SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronization clock selection bit
XI N
P45/TXD
BRG count source selection bit
1/4
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift register shift completion flag (TSC)
Transmit shift register
Transmit interrupt source selection bit
Transmit interrupt request
Character length selection bit
Transmit buffer register
Transmit buffer empty flag (TBE)
Address 001816 ^{Serial I/O1 status register Address 001916}
Data bus
Fig. 28 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer register write signal
TBE = “0”
TSC = “0”
TBE = “1”
Serial output TxD
ST
Receive buffer register read signal
TBE = “0”
D0
D1
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Serial input RxD
ST
D0
D1
TBE = “1”
SP ST D0
TSC = “1”^✽
D1
SP
✽ _{Generated at 2nd bit in 2-stop-bit mode}
(Notes 1, 2)
RBF = “1”
RBF = “0”
SP ST
D0
D1
(Notes 1, 2)
RBF = “1”
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit for reception).
2 : The serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”.
3 : Select the serial I/O1 transmit interrupt request occurrence factor between when the transmit buffer register has emptied (TBE = “1”) or
after the transmit shift operation has ended (TSC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial
I/O1 control register.
Fig. 29 Operation of UART serial I/O1 function
Rev.2.00 May. 24, 2006 page 31 of 90
REJ03B0028-0200