3803HQZ Datasheet, PDF (68/92 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3803 Group (Spec.H QzROM version)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”.
After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change
immediately after they have been written. After writing to an
interrupt request register, execute at least one instruction before
performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After
executing an ADC or SBC instruction, execute at least one
instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instruction.
• The execution of these instructions does not change the
contents of the processor status register.
A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) in the middle/high-speed mode
is at least on 500 kHz during an A/D conversion.
Do not execute the STP instruction during an A/D conversion.
D/A Converter
The accuracy of the D/A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0
V is recommended. When a D/A converter is not used, set all
values of DAi conversion registers (i=1, 2) to “0016”.
Instruction Execution Time
The instruction execution time is obtained by multiplying the
period of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is double of the XIN period in
high-speed mode.
Reserved Area, Reserved Bit
Do not write any data to the reserved area in the SFR area and the
special page. (Do not change the contents after reset.)
CPU Mode Register
Be sure to fix bit 3 of the CPU mode register (address 003B16) to
“1”.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is
“1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction
register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.)
to a direction register.
Use instructions such as LDM and STA, etc., to set the port
direction registers.
Serial Interface
In clock synchronous serial I/O, if the receive side is using an
external clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O1 continues to output the final bit from the TXD pin
after transmission is completed. SOUT2 pin for serial I/O2 goes to
high impedance after transfer is completed.
When in serial I/Os 1 and 3 (clock-synchronous mode) or in
serial I/O2, an external clock is used as synchronous clock, write
transmission data to the transmit buffer register or serial I/O2
register, during transfer clock is “H”.
Rev.1.10 Nov 14, 2005 Page 68 of 91
REJ03B0166-0110