3803HQZ Datasheet, PDF(51/92 Page) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

3803HQZ Datasheet, PDF (51/92 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

◁

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by

clearing the serial I/O3 mode selection bit (b6) of the serial I/O3

control register to â0â.

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer, but

the two buffers have the same address in a memory. Since the

shift register cannot be written to or read from directly, transmit

data is written to the transmit buffer register, and receive data is

read from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Data bus

P34/RXD3

ST detector

P36/SCLK3

Address 003016 Serial I/O3 control register Address 003216

Receive buffer register 3

Receive buffer full flag (RBF)

Character length selection bit

Receive interrupt request (RI)

7 bits

Receive shift register 3

8 bits

1/16

PE FE SP detector

Clock control circuit

UART3 control register

Address 003316

Serial I/O3 synchronous clock selection bit

f(XIN)

BRG count source selection bit

(f(XCIN) in low-speed mode)

1/4

Frequency division ratio 1/(n+1)

Baud rate generator 3

Address 002F16

ST/SP/PA generator

1/16

Transmit shift

completion flag (TSC)

P35/TXD3

Transmit shift register 3

Transmit interrupt source selection bit

Transmit interrupt request (TI)

Character length selection bit

Transmit buffer register 3

Address 003016

Transmit buffer empty flag (TBE)

Serial I/O3 status register Address 003116

Data bus

Fig 42. Block diagram of UART serial I/O3

Transmit or

receive clock

Transmit buffer

write signal

Serial output

TXD3

Receive buffer

read signal

TBE=0

TSC=0

TBE=1

TBE=0

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

TBE=1

TSC=1*

* Generated at 2nd bit in 2-stop-bit mode

RBF=1

RBF=0

RBF=1

Serial input

RXD3

Notes 1: Error flag detection occurs at the same time that the RBF flag becomes â1â (at 1st stop bit, during reception).

2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes â1â, can be selected to occur depending on the setting of the transmit interrupt source

selection bit (TIC) of the serial I/O3 control register.

3: The receive interrupt (RI) is set when the RBF flag becomes â1â.

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.

Fig 43. Operation of UART serial I/O3

Rev.1.10 Nov 14, 2005 Page 51 of 91

REJ03B0166-0110

▷