7641 Datasheet, PDF (62/138 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7641 Group
[Data Bus Buffer Status Register 0, 1 (DBBS0, DBBS1)]
004916, 004D16
The data bus buffer status registers 0, 1 consist of eight bits each.
Bits 0, 1, and 3 are read-only bits and indicate the status of the
data bus buffer. Bits 2, 4, 5, 6, and 7 are user definable flags
which can be programed, and can be read/written. The host CPU
can only read this register when the A0 pin is set to “H”.
•Bit 0: Output buffer full flag OBF0, OBF1
When writing data to the output data bus buffer, this flag is set to
“1”. When reading the output data bus buffer from the host CPU,
this flag is cleared to “0”.
•Bit 1: Input buffer full flag IBF0, IBF1
When writing data from the host CPU to the input data bus
buffer, this flag is set to “1”. When reading the input data bus
buffer from the slave CPU side, this flag is are cleared to “0”.
•Bit 3: A0 flag A00, A01
When writing data from the host CPU to the input data bus
buffer, the level of the A0 pin is latched.
[Input Data Bus Buffer Registers 0, 1 (DBBIN0, DBBIN1)]
004816, 004C16
Data on the data bus is latched to DBBIN0 or DBBIN1 by writing
request from the host CPU. Data of DBBINs can be read from the
Data Bus Buffer Registers (address 004816 or 004C16) on the
SFR area.
[Output Data Bus Buffer Registers 0, 1 (DBBOUT0,
DBBOUT1)] 004816, 004C16
When writing data to the Data Bus Buffer Registers (address
004816 or 004C16) on the SFR area, data is set to DBBOUT0 or
DBBOUT1. Data of DBBOUTs is output onto the data bus by per-
forming the reading request from the host CPU when the A0 pin is
set to “L”.
Rev.4.00 Aug 28, 2006 page 62 of 135
REJ03B0191-0400