MSP430F543X Datasheet, PDF (61/90 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F543x, MSP430F541x
MSP430F543xA, MSP430F541xA
www.ti.com.......................................................................................................................................................................................... SLAS612 – SEPTEMBER 2008
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DV_{CC(PGM/ERASE)} Program and erase supply voltage
t_READMARGIN
Read access time during margin mode
I_PGM
Supply current from DV_CC during program
I_ERASE
Supply current from DV_CC during erase
I_MERASE, I_BANK Supply current from DV_CC during mass erase or bank erase
t_CPT
Cumulative program time
t_CMErase
Cumulative mass erase time
Program/erase endurance
t_Retention
t_Word
t_{Block, 0}
t_{Block, 1–(N–1)}
Data retention duration
Word or byte program time
Block program time for first byte or word
Block program time for each additional byte or word, except for last
byte or word
t_{Block, N}
t_{Mass Erase}
t_{Seg Erase}
Block program time for last byte or word
Mass erase time
Segment erase time
TEST
CONDITIONS
See ⁽¹⁾
T_J = 25°C
See ⁽²⁾
See ⁽³⁾
See ⁽³⁾
See ⁽³⁾
See ⁽³⁾
See ⁽³⁾
MIN TYP MAX UNIT
1.8
3.6 V
200 ns
3
5 mA
2 mA
2 mA
16 ms
10
10⁴
10⁵
ms
cycles
100
years
64
85 µs
49
65 µs
37
49 µs
55
73 µs
23
32 ms
23
32 ms
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
(3) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_SBW
t_SBW,Low
t_{SBW, En}
t_SBW,Rst
f_TCK
R_internal
PARAMETER
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse length
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) ⁽¹⁾
Spy-Bi-Wire return to normal operation time
TCK input frequency - 4-wire JTAG⁽²⁾
Internal pull-down resistance on TEST
TEST
CONDITIONS
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V
3V
2.2 V/3 V
MIN
0
0.025
15
0
0
45
TYP MAX UNIT
20 MHz
15 µs
1 µs
100 µs
5 MHz
10 MHz
60
80 kΩ
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
Copyright © 2008, Texas Instruments Incorporated
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