R1QGA7236ABG Datasheet, PDF (6/39 Pages) Renesas Technology Corp – 72-Mbit QDRII+ SRAM 4-word Burst

hinS=11000.1100.1100.1100.1100
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11000.1100.1100.1100.1100---
QDR
R1QGA72 / R1QKA72 Series
Pin Descriptions
Name I/O type
Descriptions
Notes
Synchronous address inputs: These inputs are registered and must meet
SA
Input
the setup and hold times around the rising edge of K. All transactions
operate on a burst-of-four words (two clock periods of bus activity).
These inputs are ignored when device is deselected.
Synchronous read: When low, this input causes the address inputs to be
/R
Input
registered and a READ cycle to be initiated. This input must meet setup
and hold times around the rising edge of K, and is ignored on the
subsequent rising edge of K.
Synchronous write: When low, this input causes the address inputs to be
/W
Input
registered and a WRITE cycle to be initiated. This input must meet setup
and hold times around the rising edge of K, and is ignored on the
subsequent rising edge of K.
/BW_x
Input
Synchronous byte writes: When low, these inputs cause their respective
byte to be registered and written during WRITE cycles. These signals
are sampled on the same edge as the corresponding data and must meet
setup and hold times around the rising edges of K and /K for each of the
two rising edges comprising the WRITE cycle. See Byte Write Truth
Table for signal to data relationship.
Input clock: This input clock pair registers address and control inputs on
the rising edge of K, and registers data on the rising edge of K and the
K, /K Input rising edge of /K. /K is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock
rising edges. These balls cannot remain V_REF level.
Output clock: This clock pair provides a user-controlled means of tuning
device output data. The rising edge of /C is used as the output timing
reference for the first and third output data. The rising edge of C is used
C, /C
as the output timing reference for second and fourth output data. Ideally,
Input /C is 180 degrees out of phase with C. C and /C may be tied high to
1
(II only)
force the use of K and /K as the output reference clocks instead of having
to provide C and /C clocks. If tied high, C and /C must remain high and
not to be toggled during device operation. These balls cannot remain
V_REF level.
/DOFF
Input
DLL/PLL disable: When low, this input causes the DLL/PLL to be
bypassed for stable, low frequency operation.
TMS
TDI
Input
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not
connected if the JTAG function is not used in the circuit.
TCK
Input
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to V_SS if
the JTAG function is not used in the circuit.
Notes:
1. R1Q2, R1Q3, R1Q4, R1Q5, R1Q6 series have C and /C pins. R1QA, R1QB, R1QC, R1QD,
R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM, R1QN, R1QP series do not have C,
/C pins. In the series, K and /K are used as the output reference clocks instead of C and /C.
Therefore, hereafter, C and /C represent K and /K in this document.
Rev. 0.11 : 2013.01.15
R10DS0183EJ0011
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