R1EV24064ASAS0I_15 Datasheet, PDF (6/17 Pages) Renesas Technology Corp – Two-wire serial interface 64k EEPROM (8-kword  8-bit)

R1EV24064ASAS0I
Preliminary
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into
EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-
drain driven structure. Use proper resistor value for your system by considering V_OL, I_OL and the SDA pin capacitance.
Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed
during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
Data
change
change
Note: High-to-low and low-to-high change of SDA should be done during the SCL low period.
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish
each device and device address pins should be connected to V_CC or V_SS. When device address code provided from SDA
pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated.
These pins are internally pulled-down to V_SS. The device reads these pins as Low if unconnected.
Pin Connections for A0 to A2
Max connect
Pin connection
Memory size
number
A2
A1
A0
Note
64k bit
8
V_CC/V_SS
V_CC/V_SS
V_CC/V_SS
Note: 1. During floating, “V_CC/V_SS” are fixed to V_SS, because these are internally pulled-down.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following
table.
Also, acknowledgment "0" is outputted after inputting device address and memory address. After inputting write data,
acknowledgment "1""(NO ACK) is outputted.
When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated
irrespective of the WP pin status.
The WP pin is internally pulled-down to V_SS. Write operations for all memory array are allowed if unconnected.
Write Protect Area
WP pin status
V_IH
V_IL
Write protect area
64k bit
Full (64k bit)
Normal read/write operation
R10DS0127EJ0100 Rev.1.00
Nov. 09, 2012
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