R-IN32M3-EC Datasheet, PDF (6/10 Pages) Renesas Technology Corp – System LSI

RENESAS TECHNICAL UPDATE
TN-RIN-A020A/E
Data : Mar. 24, 2017
No.6 3.16.1 Features
Pin names for wait signal modified.
V4.00
Page
61 [3.16.1 Features]
Description
Page
61 [3.16.1 Features]
V4.01
Description
Remark. Each CS can be set between 1000_0000H - 1FFF_FFFFH by the programmable
SMADSEL register.
Remark. Chip select areas can be assigned to the area between addresses 1000_0000H -
1FFF_FFFFH by using the SMADSEL register (specified in 16-MB units).
- Programmable wait setting functions
 Data wait
 Write recovery wait
 Idle state
- Memory access frequency option (by dividing 100MHz signal by 2 to 6 )
- Up to four wait state signals available (WAITZ0 - WAITZ3)
- Programmable wait
- Memory access frequency (by dividing 100 MHz signal by 2 to 6 )
- Up to four wait state signals available (WAITZ, WAITZ1 to WAITZ3)
No.7 3.17.1 Features
ECC error interrupt functions added.
V4.00
Page
Description
62 [3.17.1 Features]
- 128-bit (32-bit x 4) read buffer
- Low latency :
 Read latency: 2 (1 for accessing read buffer)
 Write latency: 1
- 32-bit AHB Bus
- 128-bit RAM data bus width (without ECC circuit)
- Selectable 16- or 32-bit transfer size
- Burst transmission: single, imprecise burst, precise burst (INCR4/8/16, WRAP4/8/16)
- Little endian fixed
Page
62 [3.17.1 Features]
V4.01
Description
- 128-bit (32-bit  4) read buffer
- Latency: latency is 2 in read access in general but 1 in the case of hitting the read buffer.
latency is 1 in write access.
- AHB bus width: 32 bits
- RAM data bus width: 128 bits (without ECC circuit)
- Transfer size: 16- or 32-bit transfer selectable
- Burst transfer: single burst transfer, burst transfer of the required length, burst transfer of the fixed length
(INCR4/8/16, WRAP4/8/16)
- Little endian fixed
- ECC response: 1-bit error correction, 2-bit error detection
(c) 2017. Renesas Electronics Corporation. All rights reserved.
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