R-IN32M3-EC Datasheet, PDF (5/10 Pages) Renesas Technology Corp – System LSI

RENESAS TECHNICAL UPDATE
No.5 3.15.1 Features
Expression alignment from "state" to "wait"
V4.00
Page
60 [3.15.1 Features]
Description
- Memory controller supporting Page ROM, ROM, SRAM
- 32- or 16-bit data Bus
- Static memory control function
 Supports SRAM and peripheral devices with SRAM interface
 Page ROM support (supported CSZ0 only)
 Four chip select signals are available (CSZ0-CSZ3)
CSZ0 : Page ROM / SRAM : 1000 0000H-13FF_FFFFH (64MByte)
CSZ1 : SRAM only : 1400 0000H-17FF_FFFFH (64MByte)
CSZ2 : SRAM only : 1800 0000H-1BFF_FFFFH (64MByte)
CSZ3 : SRAM only : 1C00 0000H-1FFF_FFFFH (64MByte)
- Programmable wait function
 Address setting wait
 Data wait
 Write recovery wait
 Idle state
TN-RIN-A020A/E
Data : Mar. 24, 2017
Page
60
[3.15.1 Features]
V4.01
Description
- Memory controller supporting Page ROM, ROM, SRAM
- 32- or 16-bit data Bus
- Static memory control
 SRAM and I/O connection
 Page ROM connection (CSZ0 only)
 Four chip select signals are available (CSZ0-CSZ3)
CSZ0: Page ROM / SRAM: 1000 0000H-13FF_FFFFH (64 Mbytes)
CSZ1: SRAM only: 1400 0000H-17FF_FFFFH (64 Mbytes)
CSZ2: SRAM only: 1800 0000H-1BFF_FFFFH (64 Mbytes)
CSZ3: SRAM only: 1C00 0000H-1FFF_FFFFH (64 Mbytes)
- Programmable wait
 Address setup wait
 Data wait
 Write recovery wait
 Idle wait
(c) 2017. Renesas Electronics Corporation. All rights reserved.
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