PA2792AGR_15 Datasheet, PDF (6/14 Pages) Renesas Technology Corp – SWITCHING N- AND P-CHANNEL POWER MOS FET

μ PA2792AGR
P-channel
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Cut-off Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ^Note
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed
SYMBOL
TEST CONDITIONS
IDSS
IGSS
VGS(off)
VDS = −30 V, VGS = 0 V
VGS = m20 V, VDS = 0 V
VDS = −10 V, ID = −1 mA
| yfs |
VDS = −10 V, ID = −5 A
RDS(on)1
VGS = −10 V, ID = −5 A
RDS(on)2
VGS = −4.5 V, ID = −5 A
Ciss
VDS = −10 V,
Coss
VGS = 0 V,
Crss
f = 1 MHz
td(on)
VDD = −15 V, ID = −5 A,
tr
VGS = −10 V,
td(off)
RG = 0 Ω
tf
QG
ID = −10 A,
QGS
VDD = −24 V,
QGD
VGS = −10 V
VF(S-D)
IF = 10 A, VGS = 0 V
trr
IF = −10 A, VGS = 0 V,
Qrr
di/dt = −50 A/μs
MIN. TYP. MAX. UNIT
−10 μA
m10 μA
−1.0 −1.7 −2.5 V
6 12.9
S
14 18 mΩ
17.5 26 mΩ
2200
pF
510
pF
410
pF
12
ns
19
ns
130
ns
36
ns
47
nC
5.2
nC
15
nC
0.87 1.5 V
57
ns
41
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = −20 → 0 V
−
IAS ^BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
0 ^10%
VDS(−)
90%
VDS
VDS
Wave Form ⁰
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
4
Data Sheet G19920EJ1V0DS