PA2792AGR_15 Datasheet, PDF (5/14 Pages) Renesas Technology Corp – SWITCHING N- AND P-CHANNEL POWER MOS FET

μ PA2792AGR
ELECTRICAL CHARACTERISTICS (TA = 25°C. All terminals are connected.)
N-channel
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Zero Gate Voltage Drain Current
Gate Leakage Current
IDSS
VDS = 30 V, VGS = 0 V
IGSS
VGS = ±20 V, VDS = 0 V
10 μA
±10 μA
Gate to Source Cut-off Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
VGS(off)
| yfs |
RDS(on)1
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 5 A
VGS = 10 V, ID = 5 A
1.5 2.0 2.5 V
5
10
S
10 12.5 mΩ
RDS(on)2
VGS = 4.5 V, ID = 5 A
14.5 21 mΩ
Input Capacitance
Ciss
VDS = 10 V,
2200
pF
Output Capacitance
Coss
VGS = 0 V,
380
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
250
pF
Turn-on Delay Time
td(on)
VDD = 15 V, ID = 5 A,
9.6
ns
Rise Time
tr
VGS = 10 V,
21
ns
Turn-off Delay Time
td(off)
RG = 0 Ω
52
ns
Fall Time
tf
12
ns
Total Gate Charge
QG
ID = 10 A,
42
nC
Gate to Source Charge
QGS
VDD = 24 V,
6.2
nC
Gate to Drain Charge
Body Diode Forward Voltage ^Note
QGD
VF(S-D)
VGS = 10 V
IF = 10 A, VGS = 0 V
13
nC
0.83 1.5 V
Reverse Recovery Time
trr
IF = 10 A, VGS = 0 V,
30
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/μs
22
nC
Note Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
Data Sheet G19920EJ1V0DS
3