M66238FP Datasheet, PDF (6/15 Pages) Mitsubishi Electric Semiconductor – STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER

M66238FP
Register Configuration
1. Clock frequency setting command
Reference clock generation 12-bit division ratio, PLL synthesizer 15-bit division ratio and CKO/PLLO division ratio
are set at address (A1, A0) = (0, 0).
Data Bit
D0
0
1
D1
0
1
D2
0
1
D3
0
1
D4
0
1
D5
0
1
D6
0
1
D7
0
1
D8
0
1
D9
0
1
D10
0
1
D11
0
1
D12
0
1
D13
0
1
D14
0
1
D15
0
1
D16
0
1
D17
0
1
D18
0
1
D19
0
1
D20
0
1
D21
0
1
D22
0
1
D23
0
1
D24
0
1
D25
0
1
D26
0
1
Description
12-bit reference clock dividing ratio is set.
D11 and D0 correspond to MSB and LSB, respectively.
11
K = Σ (Dk × 2^k)
k=0
K: Reference clock dividing ratio
15-bit PLL synthesizer dividing ratio is set.
D26 and D12 correspond to MSB and LSB, respectively.
26
N = Σ (Dn × 2^n-12)
n = 12
N: PLL synthesizer dividing ratio
Default
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
REJ03F0268-0200 Rev.2.00 Mar 18, 2008
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