M66238FP Datasheet, PDF (11/15 Pages) Mitsubishi Electric Semiconductor – STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER

M66238FP
CKO/PLLO Output Frequency Range
The M66238 requires an internal VCO oscillator frequency of 25 MHz to 50 MHz.
Settings of dividing ratio K of 12-bit divider and dividing ratio N of 15-bit counter are required in order to determine
the internal VCO oscillator frequency. The relation between the settings and the internal VCO oscillator frequency is
shown below.
Oscillator frequency
fVCO =
fin × N
K
(MHz)
11
K = Σ (Dk × 2^k)
k=0
26
N = Σ (Dn × 2^n−12)
n = 12
Note:
3. Setting of fin / K ≥ 100 kHz is recommended in consideration of the frequency accuracy characteristics of
PLL output.
Therefore, set the division ratio K of the 12-bit divider and the division ratio N of the 15-bit counter to meet
the following conditions:
25 MHz ≤ fvco ≤ 50 MHz
In addition, for PLLO and CKO, setting the division ratios of the sync/division circuit (synchronous clock
generating area) to 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 will allow the frequencies of 0.78 Hz to 50 MHz to be
accommodated.
REJ03F0268-0200 Rev.2.00 Mar 18, 2008
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