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HD74LV393A Datasheet, PDF (6/11 Pages) Hitachi Semiconductor – Dual 4-bit Binary Counters
HD74LV393A
Switching Characteristics (cont)
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Pulse width
Ta = 25°C
Ta = –40 to 85°C
Symbol Min Typ Max Min
Max
fmax 75 120 — 65
—
45 65 — 35
—
tPLH/tPHL —
—
8.6 13.2 1.0
11.1 16.7 1.0
15.5
19.0
— 10.2 15.8 1.0
18.5
— 12.7 19.3 1.0
22.0
— 11.7 18.0 1.0
21.0
— 14.2 21.5 1.0
24.5
— 13.0 19.7 1.0
23.0
— 15.5 23.2 1.0
26.5
tPHL
— 7.9 12.3 1.0
14.5
— 10.4 15.8 1.0
18.0
tsu
5.0 — — 5.0
—
tw
5.0 — — 5.0
—
5.0 — — 5.0
—
Unit
MHz
ns
ns
ns
Test
Conditions
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Pulse width
Ta = 25°C
Ta = –40 to 85°C
Symbol Min Typ Max Min
Max
fmax 125 170 — 105
—
85 115 — 75
—
tPLH/tPHL —
—
5.8 8.5 1.0
7.3 10.5 1.0
10.0
12.0
— 6.8 9.8 1.0
11.5
— 8.3 11.8 1.0
13.5
— 7.7 11.2 1.0
13.0
— 9.2 13.2 1.0
15.0
— 8.5 12.5 1.0
14.5
— 10.0 14.5 1.0
16.5
tPHL
— 5.4 8.1 1.0
9.5
— 6.9 10.1 1.0
11.5
tsu
4.0 — — 4.0
—
tw
5.0 — — 5.0
—
5.0 — — 5.0
—
Unit
MHz
ns
ns
ns
Test
Conditions
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
VCC = 3.3 ± 0.3 V
FROM TO
(Input) (Output)
CLK
QA
QB
QC
QD
CLR
Qn
CLR L before CLK ↓
CLR H
CLK H or L
VCC = 5.0 ± 0.5 V
FROM TO
(Input) (Output)
CLK
QA
QB
QC
QD
CLR
Qn
CLR L before CLK ↓
CLR H
CLK H or L
Operating Characteristics
Item
Symbol
Power dissipation capacitance CPD
VCC (V)
3.3
5.0
Ta = 25°C
Min
Typ
—
12.0
—
15.0
Max
—
—
CL = 50 pF
Unit Test Conditions
pF
f = 10 MHz
Rev.3.00 Jun. 28, 2004 page 6 of 10