HD74LS166A Datasheet, PDF (6/8 Pages) Hitachi Semiconductor – 8-bit Shift Registers

HD74LS166A
Waveform
Notes:
t_{w (Clear)}
3V
Clear
Input
1.3V
1.3V
t_n ^tn ^{+ 1}
0V
t_n ^tn ^{+ 1}
3V
Clock _1.3V
Input
1.3V
1.3V
1.3V
0V
t_{w (Clock)}
t_su t_h
t_su t_h
3V
Data
Input
Output QH
1.3V
t_PHL
1.3V
1.3V
1.3V
1.3V
0V
t_PLH
t_PHL
V_OH
1.3V
1.3V
V_OL
1. Input pulse; ≤ 15 ns, t_THL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%
Clock input; t_w ≥ 20 ns
Clear inpu; t_w ≥ 20 ns, t_h = 10 ns, when testing ƒ_max, vary the clock PRR.
2. Propagation delay time (t_PLH and t_PHL) are measured at t_{n + 1}. Proper shifting of data is verified
at t_{n + 8} with a functional test.
3. t_n; bit time before clocking transition.
t_{n + 1}; bit time after one clocking transition.
t_{n + 8}; bit time after eight clocking transition.
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
Clock
Clock Inhibit
Clear
Serial Input
Shift / Load
A
B
C
Parallel ^D
Inputs _E
F
G
H
Output QH
H
L
H
L
H
L
H
H
HH L H LH L H L
Clear
Serial Shift
Load Inhibit
Serial Shift
Rev.4.00, May 10, 2006, page 6 of 7