HD74LS166A Datasheet, PDF (2/8 Pages) Hitachi Semiconductor – 8-bit Shift Registers

HD74LS166A
Function Table
Clear
Shift
Load
Inputs
Clock
Inhibit
Clock
Serial
Parallel
A…H
Internal outputs
Q_A
Q_B
Output
Q_H
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
Q_A0
Q_B0
Q_H0
H
L
L
↑
X
a…h
a
b
h
H
H
L
↑
H
X
H
Q_An
Q_Gn
H
H
L
↑
L
X
L
Q_An
Q_Gn
H
X
H
↑
X
X
Q_A0
Q_B0
Q_H0
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. a to h; the level of steady-state input at inputs A to H respectively
4. Q_A0 to Q_H0; the level of Q_A to Q_H, respectively, before the indicated steady-state input conditions were
established.
5. Q_An to Q_Gn; the level of Q_A to Q_G, respectively, before the most recent ↑ transition of the clock.
Rev.4.00, May 10, 2006, page 2 of 7