HD74HC165 Datasheet, PDF (6/8 Pages) Hitachi Semiconductor – Parallel-load 8-bit Shift Register

HD74HC165
Clock Inhibit
(Clock)
50%
V_CC
(See notes 3)
Clock
(Clock Inhibit)
t _rem
50% 50% 50%
GND
V_CC
t _su
t _w (clock)
F, H
(See notes
1 and 2)
50% 50%
50%
50%
t _su t _h
t_w(load) t _h
t _w (load)
Shift / Load
Q_H
Q_H
90%
90%
50%
10%
6ns
t _PHL
t _PLH
50%
10%
6ns
t _PHL
50%
90%
50%
10%
t _THL
t _PLH
90%
50%
10%
t _TLH
t _PHL
t _PLH
90%
50%
10%
90%
50%
10%
50%
t _TLH
t _THL
50% 50%
t _PLH
t _PHL
t _PHL
t _PLH
50%
50%
t _PLH
GND
V_CC
GND
V_CC
GND
V_OH
t _PHL
50%
V_OL
V_OH
V_OL
Notes 1. The remaining six data inputs and the serial input are low.
2. Prior to test, high-level data is loaded into H input.
3. Disable while clock is high.
4. Input pulse : PRR ≤ 1MHz, duty cycle 50%
Rev.3.00, Jan 31, 2006 page 6 of 7