HD74HC165 Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – Parallel-load 8-bit Shift Register

HD74HC165
Parallel-load 8-bit Shift Register
REJ03D0581-0300
Rev.3.00
Jan 31, 2006
Description
This 8-bit serial shift register shifts data from Q_A to Q_H when clocked. Parallel inputs to each stage are enabled by a
low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function.
Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input
high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is
inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the
register independent of the state of the clock.
Features
• High Speed Operation: t_pd (Clock to Q_H) = 21 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC165P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74HC165FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Function Table
Inputs
Parallel
Internal outputs
Shift/Load Clock Inhibit Clock
Serial
A ······ H
Q_A
Q_B
L
X
X
X
a ······h
a
b
H
L
L
X
X
Q_A0
Q_B0
H
L
H
X
H
Q_An
H
L
L
X
L
Q_An
H
H
X
X
X
Q_A0
Q_B0
Q_Ao to Q_Ho = Outputs remain unchanged.
Q_An to Q_Gn = Data shifted from the previous stage on a positive edge at the clock input.
H : High level
L : Low level
X : Irrelevant
Output
Q_H
h
Q_H0
Q_Gn
Q_Gn
Q_H0
Rev.3.00, Jan 31, 2006 page 1 of 7