HD151TS302ARP Datasheet, PDF (6/12 Pages) Renesas Technology Corp – Spread Spectrum Clock for EMI Solution

HD151TS302ARP
AC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 25°C, VDD = 3.3 V, C_L = 15 pF
Item
Symbol Min
Typ
Max
Unit Test Conditions Notes
Cycle to cycle jitter ^{*1, 2}
t_CCS
—
—
| 250 |
| 250 |
| 300 |
| 300 |
ps SSCCLKOUT,
24 MHz
SSCCLKOUT,
48 MHz
SSCOFF
SEL1:0 = 10
Fig1
—
| 250 |
| 300 |
—
| 250 |
| 300 |
SSCCLKOUT,
24 MHz
SSCCLKOUT,
48 MHz
SSC = –0.5%
SEL1:0 = 11
Fig1
—
| 250 |
| 300 |
—
| 250 |
| 300 |
SSCCLKOUT,
24 MHz
SSCCLKOUT,
48 MHz
SSC = –3.0%
SEL1:0 = 01
Fig1
Output frequency ^{*1, 2}
—
| 250 |
| 300 |
CLKOUT,
Fig1
24 MHz &
48 MHz
23.8
—
24.2
MHz SSCCLKOUT,
SSCOFF
XIN = 24 MHz
SEL1:0 = 10
47.3
—
48.7
SSCCLKOUT,
XIN = 48 MHz
23.7
—
24.2
SSCCLKOUT,
XIN = 24 MHz
SSC = –0.5%
SEL1:0 = 11
47.0
—
48.7
SSCCLKOUT,
XIN = 48 MHz
23.1
—
24.2
SSCCLKOUT,
XIN = 24 MHz
SSC = –3.0%
SEL1:0 = 01
45.9
—
48.7
SSCCLKOUT,
XIN = 48 MHz
23.8
—
24.2
CLKOUT,
24 MHz
Slew rate ^*1
t_SL
Clock duty cycle ^*1
Output impedance ^*1
47.3
—
0.8
—
45
50
—
40
48.7
CLKOUT,
48 MHz
—
V/ns @48 MHz
CLKOUT
55
%
—
Ω
0.4 V to 2.4 V
Spread spectrum
modulation frequency ^*1
—
33
—
KHz @48 MHz
SSCCLKOUT
Input clock frequency
Stabilization time ^*1,3
10
—
60
MHz
—
—
2
ms
Notes: 1. Parameters are target of design. Not 100% tested in production.
2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.
3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after
power up.
Rev.5.00, May.19.2003, page 6 of 12