3819 Datasheet, PDF (58/61 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XcIN)
tWH(XcIN)
tWL(XcIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SIN)
th(SCLK–SIN)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT4 input “H” pulse width
INT0–INT4 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
Limits
Unit
Min. Typ. Max.
2.0
µs
119
ns
30
ns
30
ns
20
µs
5.0
µs
5.0
µs
4.0
µs
1.6
µs
1.6
µs
80
ns
80
ns
1.0
µs
400
ns
400
ns
200
ns
200
ns
SWITCHING CHARACTERISTICS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol
tWH(SCLK)
Parameter
Serial I/O clock output “H” pulse width
Test conditions
CL = 100 pF
Limits
Unit
Min. Typ. Max.
tc(SCLK)
/2–160
ns
tWL(SCLK)
td(SCLK–SOUT)
tv(SCLK–SOUT)
tr(SCLK)
tf(SCLK)
tr(Pch–strg)
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output hold time
Serial I/O clock output rising time
Serial I/O clock output falling time
High-breakdown-voltage P-channel open-
drain output rising time (Note 1)
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
VEE = VCC –36 V
tc(SCLK)
/2–160
0
ns
0.2tc(SCLK) ns
ns
40
ns
40
ns
55
ns
tf(Pch–weak)
High-breakdown-voltage P-channel open-
drain output falling time (Note 2)
CL = 100 pF
VEE = VCC –36 V
1.8
µs
Notes 1 : When the bit 7 of the FLDC mode register 1 (address 003616) is at “0”.
2 : When the bit 7 of the FLDC mode register 1 (address 003616) is at “1”.
Serial clock output port
P56/SCLK3 ,
P52/SCLK2 ,
P66/SCLK11
CL
Note : Ports P8 and PA need external resistors.
Fig. ZA-2 Circuit for measuring output switching characteristics
High-breakdown-voltage
P-channel open-drain
output port
(Note)
P0, P1, P20–P23,
P3, P8, P9, PA
CL
VEE
57