3819 Datasheet, PDF(40/61 Page) Renesas Technology Corp

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3819 Datasheet, PDF (40/61 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

q Timing Setting

The digit time (Tdisp) can be set with the FLDC mode register 2

(address 003716). The Tscan and digit/segment OFF time (Toff)

can be set with the FLDC mode register 1 (address 003616).

Note that flickering will occur if the repetition frequency (1/

(Tdisp ! number of digits + Tscan)) is an integral multiple of the

digit timing Tdisp.

q FLD Automatic Display Start

To perform FLD automatic display, set the following registers.

â¢ Port P0 segment/digit switch register

â¢ Port P2 digit/port switch register

â¢ Port P8 segment/port switch register

â¢ Port PA segment/port switch register

â¢ FLDC mode register 1

â¢ FLDC mode register 2

â¢ FLD data pointer

Automatic display mode is selected by writing â1â to the bit 0 of

the FLDC mode register 2 (address 003716), and the auto-

matic display is started by writing â1â to the bit 1.

During automatic display bit 1 of the FLDC mode register 2 al-

ways keeps â1â, automatic display can be interrupted by writing

â0â to the bit 1.

q Key-scan

If key-scan is performed with the segment during the key-scan

blanking period Tscan, take the following sequence:

1. Write â0â to the bit 0 (automatic display control bit) of the

FLDC mode register 2 (address 003716).

2. Set the port corresponding to the segment for key-scan to

the output port.

3. Perform the key-scan.

4. After the key-scan is performed, write â1â (automatic display

mode) to the bit 0 of FLDC mode register 2 (address

003716).

Note on performance of key-scan in the above 1 to 4 sequence.

1. Do not write â0â to the bit 1 of FLDC mode register 2 (ad-

dress 003716).

2. Do not write â1â to the port corresponding to the digit.

G n-1

G n-2

Tdisp

Tscan

Segment

output

FLD digit interrupt occurs

at the rising edge of each digit

Digit

Segment setting by software

FLD blanking interrupt occurs

at the falling edge of the last digit

Segment

Fig. KA-7 FLDC timing

Toff

Tdisp

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