H83437 Datasheet, PDF (576/753 Pages) Renesas Technology Corp – Single-Chip Microcomputer

22.2 Sleep Mode
22.2.1 Transition to Sleep Mode
When the SSBY bit in the system control register is cleared to 0, execution of the SLEEP
instruction causes a transition from the program execution state to sleep mode. After executing the
SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The
on-chip supporting modules continue to operate normally.
22.2.2 Exit from Sleep Mode
The chip exits sleep mode when it receives an internal or external interrupt request, or a low input
at the RES or STBY pin.
Exit by Interrupt: An interrupt releases sleep mode and starts the CPU’s interrupt-handling
sequence.
If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable
bit in the module’s control register, the interrupt cannot be requested, so it cannot wake the chip
up. Similarly, the CPU cannot be awakened by an interrupt other than NMI if the I (interrupt
mask) bit is set when the SLEEP instruction is executed.
Exit by RES Pin: When the RES pin goes low, the chip exits from sleep mode to the reset state.
Exit by STBY Pin: When the STBY pin goes low, the chip exits from sleep mode to hardware
standby mode.
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