H83437 Datasheet, PDF (213/753 Pages) Renesas Technology Corp – Single-Chip Microcomputer

8.7 Application Notes
Application programmers should note that the following types of contention can occur in the free-
running timer.
Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T₃ state of a write cycle to the lower byte of the free-running counter, the clear signal
takes priority and the write is not performed.
Figure 8.16 shows this type of contention.
Write cycle:
CPU write to lower byte of FRC
T₁
T₂
T₃
ø
Internal address
bus
Internal write
signal
FRC clear signal
FRC address
FRC
N
H'0000
Figure 8.16 FRC Write-Clear Contention
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