H8S-2128 Datasheet, PDF (567/843 Pages) Renesas Technology Corp – Single-Chip Microcomputer

Section 20 Clock Pulse Generator
20.1 Overview
The H8S/2128 Series and H8S/2124 Series have a built-in clock pulse generator (CPG) that
generates the system clock (ø), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock input
circuit, and waveform shaping circuit.
20.1.1 Block Diagram
Figure 20.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
Duty
adjustment
circuit
ø_SUB
Clock
selection
circuit
Medium-speed
clock divider _{ø/2 to ø/32}
Bus master
clock
selection
circuit
ø
EXCL
Subclock
input circuit
Waveform
shaping
circuit
System clock
To ø pin
Internal clock
To supporting
modules
WDT1 count clock
Figure 20.1 Block Diagram of Clock Pulse Generator
Bus master clock
To CPU, DTC
20.1.2 Register Configuration
The clock pulse generator is controlled by the standby control register (SBYCR) and low-power
control register (LPWRCR). Table 20.1 shows the register configuration.
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