H838099 Datasheet, PDF (562/736 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series

Section 24 Address Break
24.1.2 Address Break Status Register 2 (ABRKSR2)
ABRKSR2 consists of the address break interrupt flag and the address break interrupt enable bit.
Bit
7
6
5 to 0
Initial
Bit Name Value R/W
ABIF2
0
R/W
ABIE2
0
R/W
—
All 1 —
Description
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR2 is satisfied
[Clearing condition]
When 0 is written after ABIF2=1 is read
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
24.1.3 Break Address Registers 2 (BAR2E, BAR2H, BAR2L)
BAR2E, BAR2H, and BAR2L are 24-bit read/write registers that set the address for generating an
address break interrupt. When setting the address break condition to the instruction execution
cycle, set the first byte address of the instruction. The initial value of this register is H'FFFFFF.
24.1.4 Break Data Registers 2 (BDR2H, BDR2L)
BDR2H and BDR2L are 16-bit read/write registers that set the data for generating an address
break interrupt. BDR2H is compared with the upper 8-bit data bus. BDR2L is compared with the
lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is
used for even and odd addresses in the data transmission. Therefore, comparison data must be set
in BDR2H for byte access. For word access, the data bus used depends on the address. See section
24.1.1, Address Break Control Register 2 (ABRKCR2), for details. The initial value of this
register is undefined.
Rev. 2.00 Jul. 04, 2007 Page 522 of 692
REJ09B0309-0200