H8S-2168 Datasheet, PDF (561/874 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

16.3.3 Host Interface Control Register 4 (HICR4)
HICR4 controls the selection of access channel when setting addresses for LPC channels 1 and 2,
and the operation of KCS, SMIC, and BT interfaces included in channel 3.
R/W
Bit Bit Name Initial Value Slave Host Description
7 LADR12SEL 0
R/W  Switches the access channel of LADR12H,
LAD12L.
0: LADR1 is selected
1: LADR2 is selected
6 to 4 
All 0
R/W  Reserved
The initial value should not be changed.
3 SWENBL 0
R/W 
In BT mode, H'5 (short wait) or H'6 (long wait) is
returned to the host in the synchronized return
cycle from slave, thus can make the host wait.
0: Short wait is issued
1: Long wait is issued
2 KCSENBL 0
R/W 
Enables or disables the use of the KCS interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: KCS interface operation is disabled
No address (LADR3) matches for IDR3, ODR3,
or STR3 in KCS mode
1: KCS interface operation is enabled
1 SMICENBL 0
R/W 
Enables or disables the use of the SMIC interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: SMIC interface operation is disabled
No address (LADR3) matches for SMICFLG,
SSMICCSR, or SMICDTR
1: SMIC interface operation is enabled
0 BTENBL 0
R/W 
Enables or disables the use of the BT interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: BT interface operation is disabled
No address (LADR3) matches for BTIMSR,
BTCR, or BTDTR
1: BT interface operation is enabled
Rev. 3.00, 03/04, page 521 of 830