H8S-2168 Datasheet, PDF (486/874 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

15.3.6 I²C Bus Control Register (ICCR)
ICCR controls the I²C bus interface and performs interrupt flag confirmation.
Initial
Bit Bit Name Value
7
ICE
0
6
IEIC
0
5
MST
0
4
TRS
0
R/W Description
R/W I²C Bus Interface Enable
0: I²C bus interface modules are stopped and I²C bus
interface module internal state is initialized. SAR and
SARX can be accessed.
1: I²C bus interface modules can perform transfer and
reception, they are connected to the SCL and SDA pins,
and the I²C bus can be driven. ICMR and ICDR can be
accessed.
R/W I²C Bus Interface Interrupt Enable
0: Disables interrupts from the I²C bus interface to the CPU
1: Enables interrupts from the I²C bus interface to the CPU.
R/W Master/Slave Select
R/W _{Transmit/Receive Select}
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they lose
in a bus contention in master mode of the I²C bus format.
In slave receive mode with I²C bus format, the R/W bit in
the first frame immediately after the start condition
automatically sets these bits in receive mode or transmit
mode by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
Rev. 3.00, 03/04, page 446 of 830