H8S29 Datasheet, PDF (554/1304 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T₂ state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 10.49 shows the timing in this case.
TCNT write cycle
T₁
T₂
φ
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 10.49 Contention between TCNT Write and Clear Operations
Rev.6.00 Sep. 27, 2007 Page 522 of 1268
REJ09B0220-0600