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H8S29 Datasheet, PDF (228/1304 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer
Section 6 Bus Controller
φ
RTCNT
N
H'00
RTCOR
N
Refresh request signal
and CMF bit setting signal
Figure 6.24 Compare Match Timing
TRp
TRr
TRc1
TRc2
φ
CS (RAS)
CAS, LCAS
Note: n = 2 to 5
Figure 6.25 CBR Refresh Timing
When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS
signal should be adjusted with bits RLW1 and RLW0. These bits are only enabled in refresh
operations.
Figure 6.26 shows the timing when the RCW bit is set to 1.
Rev.6.00 Sep. 27, 2007 Page 196 of 1268
REJ09B0220-0600