R8C14 Datasheet, PDF (54/277 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C/Tiny SERIES

R8C/14 Group, R8C/15 Group
9. Clock Generation Circuit
Oscillation Stop Detection Register⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol
Address
After Reset
OCD
000Ch
04h
Bit Symbol
Bit Name
Function
RW
Oscillation Stop Detection
b1 b0
OCD0 ^{Enable Bit}
0 0 : Oscillation stop detection function
RW
disabled
0 1 : Do not set
OCD1
1 0 : Do not set
1 1 : Oscillation stop detection function
RW
enabled^(4,7)
System Clock Select Bit⁽⁶⁾
0 : Selects main clock⁽⁷⁾
OCD2
1 : Selects on-chip oscillator clock⁽²⁾
RW
Clock Monitor Bit^(3,5)
0 : Main clock oscillates
OCD3
1 : Main clock stops
RO
—
Reserved Bit
Set to “0”
(b7-b4)
RW
NOTES :
1. Set the PRC0 bit in the PRCR register to “1” (w rite enable) before rew riting to this register.
2. The OCD2 bit is automatically set to “1” (selects on-chip oscillator clock) if a main clock oscillation stop is detected
w hile the OCD1 to OCD0 bits are set to “11b” (oscillation stop detection function enabled). If the OCD3 bit is set to “1”
(main clock stops), the OCD2 bit remains unchanged w hen w riting “0” (selects main
clock).
3. The OCD3 bit is enabled w hen the OCD1 to OCD0 bits are set to “11b”.
4. Set the OCD1 to OCD0 bits to “00b” (oscillation stop detection function disabled) before entering stop and on-chip
oscillator mode (main clock stops).
5. The OCD3 bit remains “0” (main clock oscillates) if the OCD1 to OCD0 bits are set to “00b”.
6. The CM14 bit is set to “0” (low -speed on-chip oscillator on) if the OCD2 bit is set to “1” (selects on-chip oscillator
clock).
7. Refer to Figure 9.9 Procedure of Sw itching Clock Source From Low -Speed On-Chip Oscillator to Main
Clock for the sw itching procedure w hen the main clock re-oscillates after detecting an oscillation stop.
Figure 9.4 OCD Register
Rev.2.10 Jan 19, 2006 Page 42 of 253
REJ09B0164-0210