R8C14 Datasheet, PDF (147/277 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C/Tiny SERIES

R8C/14 Group, R8C/15 Group
14. Serial Interface
14.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmit and receive data after setting the desired bit rate and transfer data
format. Table 14.4 lists the Specification of UART Mode. Table 14.5 lists the Registers to Be Used and
Settings in UART Mode.
Table 14.4 Specification of UART Mode
Item
Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Generation Timing
Error Detection
Specification
• Character bit (transfer data): selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: selectable from odd, even, or none
• Stop bit: selectable from 1 or 2 bits
• CKDIR bit in U0MR register is set to “0” (internal clock) : fj/(16(n+1))
fj=f1, f8, f32 n=setting value in U0BRG register: 00h to FFh
• CKDIR bit is set to “1” (external clock) : fEXT/(16(n+1))
fEXT: input from CLK0 pin n=setting value in U0BRG register: 00h to FFh
• Before transmit starts, the following are required
- TE bit in U0C1 register is set to “1” (transmit enabled)
- TI bit in U0C1 register is set to “0” (data in U0TB register)
• Before receive starts, the following are required
- RE bit in U0C1 register is set to “1” (receive enabled)
- Detects start bit
• When transmitting, one of the following conditions can be selected
- U0IRS bit is set to “0” (transmit buffer empty):
when transferring data from the U0TB register to UART0 transmit
register (when transmit starts)
- U0IRS bit is set to “1” (transfer ends):
when serial interface completes transmitting data from the UART0
transmit register
• When receiving
When transferring data from the UART0 receive register to U0RB
register (when receive ends)
• Overrun error⁽¹⁾
This error occurs if serial interface starts receiving the following data
before reading the U0RB register and receiving the bit one before the last
stop bit of the following data
• Framing error
This error occurs when the number of stop bits set are not detected
• Parity error
This error occurs when parity is enabled, the number of 1’s in parity and
character bits do not match the number of 1’s set
• Error sum flag
This flag is set is set to “1” when any of the overrun, framing, and parity
errors is generated
NOTES:
1. If an overrun error occurs, the value in the U0RB register will be indeterminate. The IR bit in the
S0RIC register remains unchanged.
Rev.2.10 Jan 19, 2006 Page 135 of 253
REJ09B0164-0210