H8S2609 Datasheet, PDF (516/624 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 17 ROM
Start
*1
Set SWE bit in FLMCR1
Wait (t_sswe) µs
n=1
Set EBR1 or EBR2
Perform erasing in block units.
*5
*3 *4
Enable WDT
Set ESU bit in FLMCR1
Wait (t_sesu) µs
Set E bit in FLMCR1
Wait (t_se) ms
Clear E bit in FLMCR1
Wait (t_ce) µs
Clear ESU bit in FLMCR1
Wait (t_cesu) µs
Disable WDT
*5
Start of erase
*5
Erase halted
*5
*5
Set EV bit in FLMCR1
Wait (t_sev) µs
*5
Set block start address as verify address
n←n+1
H'FF dummy write to verify address
Wait (t_sevr) µs
*5
Increment
address
No
Read verify data
Verify data = all 1s?
Yes
Last address of block?
Yes
Clear EV bit in FLMCR1
*2
No
*5
Wait (t_cev) µs
Clear SWE bit in FLMCR1
*5
Wait (t_cswe) µs
End of erasing
Clear EV bit in FLMCR1
*5
Wait (t_cev) µs
*5
n ≥ (N)?
Yes
Clear SWE bit in FLMCR1
No
*5
Wait (t_cswe) µs
Erase failure
Notes: 1.
2.
3.
4.
5.
Prewriting (setting erase block data to all 0s) is not necessary.
Verify data is read in 16-bit (word) units.
Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.
Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
The wait times and the value of N are shown in section 21.5, Flash Memory Characteristics.
Figure 17.10 Erase/Erase-Verify Flowchart
Rev. 1.00 Jan. 25, 2008 Page 482 of 586
REJ09B0428-0100