3803_03 Datasheet, PDF (51/136 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3803/3804 Group
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
P44/RXD1
P46/SCLK1
Address 001816
Serial I/O1 control register Address 001A16
OE
Receive buffer register 1
Character length selection bit
ST detector 7 bits
Receive shift register 1
8 bits
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
PE FE SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronous clock selection bit
BRG count source selection bit
f(XIN)
(f(XCIN) in low-speed mode)
1/4
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
P45/TXD1
Transmit shift register 1
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register 1
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 42 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD1
ST
Receive buffer read
signal
TBE=0
D0
D1
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Serial input RXD1
ST
D0
D1
TBE=1
SP
ST
D0
T S C = 1^]
D1
SP
]
Generated at 2nd bit in 2-stop-bit mode
RBF=1
SP
ST
RBF=0
D0
D1
RBF=1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
Fig. 43 Operation of UART serial I/O1
Rev.4.01 Nov 14, 2003 page 51 of 136