HN58X2408FPIAG Datasheet, PDF (5/21 Pages) Renesas Technology Corp – Two-wire serial interface 8k EEPROM (1-kword × 8-bit)/16k EEPROM (2-kword × 8-bit) 32k EEPROM (4-kword × 8-bit)/64k EEPROM (8-kword × 8-bit)

HN58X2408/HN58X2416/HN58X2432/HN58X2464FPIAG
AC Characteristics (Ta = −40 to +85°C, V_CC = 1.8 to 5.5 V)
Test Conditions
• Input pules levels:
 V_IL = 0.2 × V_CC
 V_IH = 0.8 × V_CC
• Input rise and fall time: ≤ 20 ns
• Input and output timing reference levels: 0.5 × V_CC
• Output load: TTL Gate + 100 pF
Parameter
Symbol Min
Typ
Max
Unit
Clock frequency
f_SCL


400
kHz
Clock pulse width low
t_LOW
1200 

ns
Clock pulse width high
t_HIGH
600


ns
Noise suppression time
t_I


50
ns
Access time
t_AA
100

900
ns
Bus free time for next mode
t_BUF
1200 

ns
Start hold time
t_HD.STA
600


ns
Start setup time
t_SU.STA
600


ns
Data in hold time
t_HD.DAT
0


ns
Data in setup time
t_SU.DAT
100


ns
Input rise time
t_R


300
ns
Input fall time
t_F


300
ns
Stop setup time
t_SU.STO
600


ns
Data out hold time
t_DH
50


ns
Write cycle time
V_CC = 2.7 V to 5.5 V t_WC


10
ms
V_CC = 1.8 V to 2.7 V t_WC


15
ms
Notes: 1. This parameter is sampled and not 100% tested.
2. t_WC is the time from a stop condition to the end of internally controlled write cycle.
Notes
1
1
1
2
2
Rev.3.00, Dec.21.2004, page 5 of 19