HD74HC166 Datasheet, PDF (5/7 Pages) Hitachi Semiconductor – Parallel-load 8-bit Shift Register

HD74HC166
Test Circuit
Measurement point
C_L*
Note: C_L includes the probe and fig capacitance.
Waveforms
tW
Clear
Clock
Data
Output QH
50%
50%
tn ^tn+1
tn ^tn+1
50%
50%
50%
tW
tsu th
50%
tsu th
50%
tPHL
50%
50%
tPLH
50%
50%
50%
tPHL
50%
V_CC
0V
V_CC
0V
V_CC
0V
VOH
VOL
Notes 1. Input wavwform : PRR ≤ 1 MHz㧘Zo = 50 Ω㧘t_r ≤ 6 ns㧘t_f ≤ 6 ns
2. Propagation delay time (tPLH and tPHL)are measured at tn+1.
Proper shifting of data is verified at tn+8 with a functional test.
3. tn : bit time before clocking transition.
ޓtn+1 : bit time after one clocking transition.
ޓtn+8 : bit time after eight clocking transition.
Rev.3.00, Jan 31, 2006 page 5 of 6