HD74HC166 Datasheet, PDF (1/7 Pages) Hitachi Semiconductor – Parallel-load 8-bit Shift Register

HD74HC166
Parallel-load 8-bit Shift Register
REJ03D0582-0300
Rev.3.00
Jan 31, 2006
Description
This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the
Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is
asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the
clock inputs to act as a clock inhibit.
Features
• High Speed Operation: t_pd (Clock to Q_H) = 14 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC166P
DILP-16 pin
PRDP0016AE-B _P
(DP-16FV)
HD74HC166FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Function Table
Inputs
Clock
Parallel
Internal outputs
Clear Shift/Load
Inhibit
Clock
Serial
A ··· H
Q_A
Q_B
L
X
X
X
X
X
L
L
H
X
L
L
X
X
Q_A0
Q_B0
H
L
L
X
a ··· h
a
b
H
H
L
H
X
H
Q_An
H
H
L
L
X
L
Q_An
H
X
H
X
X
Q_A0
Q_B0
Q_Ao to Q_Ho = Outputs remain unchanged.
Q_An to Q_Gn = Data shifted from the previous stage on a positive edge at the clock input.
H : High level
L : Low level
X : Irrelevant
Output
Q_H
L
Q_H0
h
Q_Gn
Q_Gn
Q_H0
Rev.3.00, Jan 31, 2006 page 1 of 6