HD74HC131 Datasheet, PDF (5/9 Pages) Hitachi Semiconductor – 3-to-8-line Decoder/Demultiplexer with Edge-Triggered Address Registers

HD74HC131
Switching Characteristics (C_L = 50 pF, Input t_r = t_f = 6 ns)
Item
Propagation delay
time
Pulse width
Setup time
Hold time
Output rise/fall
time
Input capacitance
Symbol VCC (V)
tPLH, tPHL 2.0
4.5
6.0
tPLH, tPHL 2.0
4.5
6.0
tw
2.0
4.5
6.0
tsu
2.0
4.5
6.0
th
2.0
4.5
6.0
tTLH, tTHL 2.0
4.5
6.0
Cin
—
Ta = 25°C
Ta = –40 to +85°C
Min Typ Max Min Max Unit
Test Conditions
— — 210 —
265 ns CLK to Y
— 20 42
—
53
— — 36
—
45
— — 140 —
175 ns G1 or G2 to Y
— 15 28
—
35
— — 24
—
30
80 — — 100
— ns
16 5 —
20
—
14 — —
17
—
50 — —
65
— ns
10 2 —
13
—
9 ——
11
—
5 ——
5
— ns
5 –1 —
5
—
5 ——
5
—
— — 75
—
95 ns
— 5 15
—
19
— — 13
—
16
— 5 10
—
10 pF
Test Circuit
Measurement point
C_L*
Note: C_L includes the probe and fig capacitance.
Rev.2.00, Oct 11, 2005 page 5 of 8