HD74HC131 Datasheet, PDF (2/9 Pages) Hitachi Semiconductor – 3-to-8-line Decoder/Demultiplexer with Edge-Triggered Address Registers

HD74HC131
Function Table
Inputs
Enable
Select
CLK G1
G2
C
B
A
X
X
H
X
X
X
X
L
X
X
X
X
H
L
L
L
L
H
L
L
L
H
H
L
L
H
L
H
L
L
H
H
H
L
H
L
L
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
H
L
X
X
X
H : High level
L : Low level
X : Irrelevant
Pin Arrangement
Outputs
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
Outputs corresponding to stored address, L; all others H
A1
B2
C3
CLK 4
G2 5
G1 6
Y7 7
GND 8
(Top view)
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
Rev.2.00, Oct 11, 2005 page 2 of 8