HD74CDCF2509B Datasheet, PDF (5/9 Pages) Hitachi Semiconductor – 140 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver

HD74CDCF2509B
Pin Function
Pin name
No.
CLK
24
Type
I
FBIN
13
I
1G
2G
FBOUT
1Y(0:4)
2Y(0:3)
AV_CC
11
I
14
I
12
O
3, 4, 5, 8, 9 O
16, 17, 20, O
21
23
Power
AGND
V_CC
GND
1
Ground
2, 10, 15, 22 Power
6, 7, 18,19 Ground
Description
Clock input. CLK provides the clock signal to be distributed by the
HD74CDCF2509B clock driver. CLK is used to provide the reference signal to
the integrated PLL that generates the clock output signals. CLK must have a
fixed frequency and fixed phase for the PLL to obtain phase lock. Once the
circuit is powered up and a valid CLK signal is applied, a stabilization time is
required for the PLL to phase lock the feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN
must be hard-wired to FBOUT to complete the PLL. The integrated PLL
synchronizes CLK and FBIN so that there is nominally zero phase error
between CLK and FBIN.
Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is
low, outputs 1Y(0:4)are disabled to a logic-low state. When 1G is high, all
outputs 1Y(0:4) are enabled and switch at the same frequency as CLK.
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is
low, outputs 2Y(0:3)are disabled to a logic low state. When 2G is high, all
outputs 2Y(0:3) are enabled and switch at the same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at
the same frequency as CLK. When externally wired to FBIN, FBOUT
completes the feedback loop of the PLL.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank
1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic
low state by deasserting the 1G control input.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank
2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic
low state by deasserting the 2G control input.
Analog power supply. AV_CC provides the power reference for the analog
circuitry. In addition, AV_CC can be used to bypass the PLL for test purposes.
When AV_CC is strapped to ground, PLL is bypassed. This bypass mode is
used for Hitachi test.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply
Ground
Electrical Characteristics
Item
Symbol Min Typ ^*1 Max
Unit
Test Conditions
Input clamp voltage
Output voltage
V_IK
—
—
V_OH V_CC–0.2 —
–1.2
—
V V_CC = 3 V, I_I = –18 mA
V V_CC = Min to Max, I_OH = –100 µA
2.1
—
—
V_CC = 3 V, I_OH = –12 mA
2.4
—
—
V_OL
—
—
0.2
V_CC = 3 V, I_OH = –6 mA
V_CC = Min to Max, I_OL = 100 µA
—
—
0.8
V_CC = 3 V, I_OL = 12 mA
—
—
0.55
V_CC = 3 V, I_OL = 6 mA
Input current
I_IN
—
—
±5
µA V_CC = 3.6 V, V_IN = V_CC or GND
Quiescent supply current
I_CC
—
—
10
µA AV_CC = GND, V_CC = 3.6 V,
V_I = V_CC or GND, I_O = 0
∆I_CC
—
—
500
µA AV_CC = GND, V_CC = 3.3 to 3.6 V
One input at V_CC–0.6 V,
Other inputs at V_CC or GND
Input capacitance
C_IN
—
4
—
pF V_CC = 3.3 V, V_I = V_CC or GND
Output capacitance
C_O
—
6
—
pF V_CC = 3.3 V, V_O = V_CC or GND
Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating
conditions.
Rev.10.00 Apr 07, 2006 page 5 of 8