HD74ACT161 Datasheet, PDF (5/9 Pages) Hitachi Semiconductor – Synchronous Presettable Binary Counter

HD74ACT161/HD74ACT163
AC Characteristics: HD74ACT161
Ta = +25°C
Ta = –40°C to +85°C
Item
Maximum count
frequency
Symbol V_CC (V)*¹
f_max
5.0
C_L = 50 pF
Min Typ Max
115 125 —
C_L = 50 pF
Min
Max
100
—
MHz
Unit
Propagation delay
t_PLH
5.0
CP to Q_n (PE Input
HIGH or LOW)
1.0 5.5 9.5 1.0
10.5
ns
Propagation delay
t_PLH
5.0
CP to Q_n (PE Input
HIGH or LOW)
1.0 6.0 10.5 1.0
11.5
ns
Propagation delay
t_PLH
5.0
CP to TC
1.0 7.0 11.0 1.0
12.5
ns
Propagation delay
t_PHL
5.0
CP to TC
1.0 8.0 12.5 1.0
13.5
ns
Propagation delay
t_PLH
5.0
CET to TC
1.0 5.5 8.5 1.0
10.0
ns
Propagation delay
t_PHL
5.0
CET to TC
1.0 6.0 9.5 1.0
10.5
ns
Propagation delay
t_PHL
5.0
MR to Q_n
Propagation delay
t_PHL
5.0
MR to TC
1.0 6.0 10.0 1.0
1.0 8.0 13.5 1.0
11.0
ns
14.5
ns
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74ACT161
Ta = –40°C
Ta = +25°C
to +85°C
Item
Set-up time, HIGH or LOW
P_n to CP
Hold time, HIGH or LOW
P_n to CP
Setup time, HIGH or LOW
MR to CP
C_L = 50 pF
C_L = 50 pF
Symbol V_CC (V)*¹
Typ
Guaranteed Minimum
t_su
5.0
4.0
9.5
11.5
ns
t_h
5.0
–5.0
0
0
ns
t_su
5.0
4.0
8.5
9.5
ns
Unit
Hold time, HIGH or LOW
t_h
5.0
–5.5
–0.5
–0.5
ns
MR to CP
Setup time, HIGH or LOW
t_su
5.0
4.0
8.5
9.5
ns
PE to CP
Hold time, HIGH or LOW
t_h
5.0
–5.5
–0.5
–0.5
ns
PE to CP
Setup time, HIGH or LOW
t_su
5.0
2.5
5.5
6.5
ns
CEP or CET to CP
Hold time, HIGH or LOW
t_h
5.0
–3.0
0
0
ns
CEP or CET to CP
Clock pulse width (Load)
t_w
5.0
2.0
3.0
3.5
ns
HIGH or LOW
Clock pulse width (Count)
t_w
5.0
2.0
3.0
3.5
ns
HIGH or LOW
MR pulse width, LOW
t_w
5.0
3.0
3.0
7.5
ns
Recovery time MR to CP
t_rec
5.0
0
0
0.5
ns
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 8