HD74ACT161 Datasheet, PDF (3/9 Pages) Hitachi Semiconductor – Synchronous Presettable Binary Counter

HD74ACT161/HD74ACT163
Mode Select Table
SR*¹
PE
CET
L
X
X
H
L
X
H
H
H
H
H
L
H
H
X
Note: 1. For HD74ACT163
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
State Diagram
0
CEP
X
X
H
X
L
Action on the Rising Clock Edge ( )
Reset (Clear)
Load (Pn → Qn)
Count (Increment)
No change (Hold)
No change (Hold)
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
Block Diagram
PE
CEP
CET
’161 ’163
’163
ONRY
P0
P1
P2
P3
TC
CP
CP
’161
CP
ONRY
D CP D
CD _{Q Q}
Q0
Q0
DETAIL A
DETAIL A
DETAIL A
DETAIL A
MR ’161
SR ’163
Q0
Q1
Q2
Q3
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 3 of 8