HD74AC107 Datasheet, PDF (5/7 Pages) Hitachi Semiconductor – Dual JK Flip-Flop (with Separate Clear and Clock)

HD74AC107/HD74ACT107
Operating Requirements: HD74AC107
Ta = –40°C
Ta = +25°C
to +85°C
C_L = 50 pF
C_L = 50 pF
Item
Symbol V_CC (V)*¹
Typ
Guaranteed Minimum
Setup time
t_su
3.3
3.0
5.5
6.0
ns
J or k to C_P
5.0
2.0
4.0
4.5
Hold time
t_h
3.3
–1.5
0.0
0.0
C_P to J or k
5.0
–0.5
0.0
0.0
Pulse width
t_w
3.3
2.0
5.5
7.0
C_P or C_D
5.0
2.0
4.5
5.0
Recovery time
t_rec
3.3
1.5
3.0
3.0
C_D to C_P
5.0
1.0
3.0
3.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Unit
AC Characteristics: HD74ACT107
Item
Maximum clock
frequency
Symbol V_CC (V)*¹
f_max
5.0
Propagation delay
t_PLH
5.0
C_P to Q or Q
Propagation delay
t_PHL
5.0
C_P to Q or Q
Propagation delay
t_PLH
5.0
C_D to Q
Propagation delay
t_PHL
5.0
C_D to Q
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = +25°C
C_L = 50 pF
Min Typ Max
100 —
—
1.0 9.5 12.5
1.0 10.5 13.0
1.0 8.5 11.0
1.0 8.5 11.0
Ta = –40°C to +85°C
C_L = 50 pF
Min
Max
80
—
MHz
1.0
13.5
ns
1.0
14.0
1.0
12.0
1.0
12.0
Unit
Operating Requirements: HD74ACT107
Ta = –40°C
Ta = +25°C
to +85°C
Item
Symbol V_CC (V)*¹
C_L = 50 pF
C_L = 50 pF
Typ
Guaranteed Minimum
Setup time
J or k to C_P
t_su
5.0
2.5
7.0
8.0
ns
Hold time
C_P to J or k
t_h
5.0
0.0
1.5
1.5
Pulse width
C_P or C_D
t_w
5.0
4.5
7.0
8.0
Recovery time
C_D to C_P
t_rec
5.0
—
3.0
3.0
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Unit
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C_IN
C_PD
Typ
4.5
35.0
Unit
pF
pF
V_CC = 5.5 V
V_CC = 5.0 V
Condition
Rev.2.00, Jul.16.2004, page 5 of 6