HD74AC107 Datasheet, PDF (2/7 Pages) Hitachi Semiconductor – Dual JK Flip-Flop (with Separate Clear and Clock)

HD74AC107/HD74ACT107
Logic Symbol
1 J₁
Q₁ ^{3 8} J₂
Q₂ 6
12 CP₁
9 _CP2
4
K_{1 CD1} Q₁ ^{2 11} K_{2 CD2} Q₂
5
13 _{VCC = Pin14} 10
GND = Pin7
Pin Names
J₁, J₂, K₁, K₂
CP₁, CP₂
C_D1, C_D2
Q₁, Q₂, Q₁, Q ₂
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active Low)
Outputs
Truth Table
Inputs
@ t_n
J
K
L
L
Qn
L
H
L
H
L
H
H
H
Qn
H
: High Voltage Level
L
: Low Voltage Level
t_n
: Bit time before clock pulse.
t_{n + 1} : Bit time after clock pulse.
Logic Diagram
C_D
J
#CP
#CP
K
CP
#CP
CP
#CP
Outputs
@ t_{n + 1}
Q
Q
Q
CP
CP
CP
CP
CP
Rev.2.00, Jul.16.2004, page 2 of 6