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BB506C_11 Datasheet, PDF (5/9 Pages) Renesas Technology Corp – Built in Biasing Circuit MOS FET IC
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BB506C
Power Gain vs. Gate Resistance
50
VDS = 5 V
VG1 = 5 V
40
VG2S = 4 V
f = 900 MHz
30
20
10
0
10
100
1000
Gate Resistance RG (kΩ)
Power Gain vs.
Gate2 to Source Voltage
25
20
15
10
VDS = 5 V
5
VG1 =5 V
RG = 100 kΩ
f = 900 MHz
0
1
2
3
4
Gate2 to Source Voltage VG2S (V)
Gain Reduction vs.
Gate2 to Source Voltage
40
35
VDS = 5 V
VG1 = 5 V
30
RG = 100 kΩ
f = 900 MHz
25
20
15
10
5
0
0
1
2
3
4
Gate2 to Source Voltage VG2S (V)
Preliminary
Noise Figure vs. Gate Resistance
5
VDS = 5 V
VG1 = 5 V
4
VG2S = 4 V
f = 900 MHz
3
2
1
0
10
100
1000
Gate Resistance RG (kΩ)
Noise Figure vs.
5
Gate2 to Source Voltage
VDS = 5 V
VG1 = 5 V
4
RG = 100 kΩ
f = 900 MHz
3
2
1
0
1
2
3
4
Gate2 to Source Voltage VG2S (V)
R07DS0288EJ0200 Rev.2.00
Mar 28, 2011
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