2SK1859 Datasheet, PDF (5/7 Pages) Hitachi Semiconductor – Silicon N-Channel MOS FET

2SK1859
Reverse Drain Current vs.
Source to Drain Voltage
10
Pulse Test
8
6
4
2
5 V, 10 V
V_GS = 0, –5 V
0
0.4 0.8 1.2 1.6 2.0
Source to Drain Voltage V_SD (V)
Normalized Transient Thermal Impedance vs. Pulse Width
3
1 ^D=1
0.5
0.3 _0.2
0.1 ^0.1
0.05
0.03
0.01
0.02
0.01 _{1 Shot Pulse}
10 µ
100 µ
1m
10 m
Pulse Width PW (S)
θch – c(t) = γs(t) • θch – c
θch – c = 2.08°C/W, Tc = 25°C
P_DM
PW
T
D
=
PW
T
100 m
1
10
Switching Time Test Circuit
Vin Monitor
D.U.T
Vout Monitor
R_L
Vin
10 V
50 Ω
V_DD
= 30 V
Waveforms
Vin _10%
Vout ^10%
t_{d (on)}
90%
t_r
90%
90%
t_{d (off)}
10%
t_f
Rev.2.00 Sep 07, 2005 page 5 of 6