2SJ546 Datasheet, PDF (5/8 Pages) Hitachi Semiconductor – Silicon P Channel MOS FET High Speed Power Switching

2SJ546
Reverse Drain Current vs.
Source to Drain Voltage
–20
–16
–10 V
–12
–5 V
–8
–4
V_GS = 0, 5 V
Pulse Test
0
0 –0.4 –0.8 –1.2 –1.6 –2.0
Source to Drain Voltage V_SD (V)
Maximum Avalanche Energy vs.
Channel Temperature Derating
20
I_AP = –15 A
V_DD = –25 V
16
duty < 0.1 %
Rg ≥ 50 Ω
12
8
4
0
25 50
75 100 125 150
Channel Temperature Tch (°C)
Normalized Transient Thermal Impedance vs. Pulse Width
3
D=1
1
0.5
Tc = 25°C
0.3
0.2
0.1
0.1
0.05
0.02
0.03
0.011shot pulse
0.01
10 µ
100 µ
θch – c (t) = γ s (t) • θch – c
θch – c = 4.17°C/W, Tc = 25°C
P_DM
D = ^PW
T
PW
T
1m
10 m
100 m
1
10
Pulse Width PW (S)
Vin
–15 V
Avalanche Test Circuit
V_DS
Monitor
Rg
50 Ω
L
I_AP
Monitor
D.U.T
V_DD
Avalanche Waveform
E_AR =
1
2
• L • I_AP2 •
V_DSS
V_DSS – V_DD
I_AP
I_D
V_(BR)DSS
V_DS
V_DD
0
Rev.3.00 Sep 07, 2005 page 5 of 7