2SJ471 Datasheet, PDF (5/7 Pages) Hitachi Semiconductor – Silicon P Channel DV-L MOS FET High Speed Power Switching

2SJ471
Reverse Drain Current vs.
Source to Drain Voltage
–50
Pulse Test
–40
–10 V
–30
–5 V
–20
V_GS = 0, 5 V
–10
0
0 –0.4 –0.8 –1.2 –1.6 –2.0
Source to Drain Voltage V_SD (V)
Normalized Transient Thermal Impedance vs. Pulse Width
3
D=1
1
0.5
Tc = 25°C
0.3
0.2
0.1
0.1
0.05
0.02
0.03
0.01 _1shot ^pulse
0.01
10 µ
100 µ
θch – c (t) = γ s (t) • θch – c
θch – c = 4.17°C/W, Tc = 25°C
P_DM
D=
PW
T
PW
T
1m
10 m
100 m
1
10
Pulse Width PW (S)
Switching Time Test Circuit
Vin Monitor
D.U.T.
Vout
Monitor
R_L
Vin
10 V
50 Ω
V_DD
= –10 V
Waveform
Vin
10%
90%
90%
90%
Vout
td(on)
10%
tr
td(off)
10%
tf
Rev.2.00 Sep 07, 2005 page 5 of 6